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ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 ddr sdram registered module 184pin registered module based on 512mb b-die with 1,700 / 1,200mil height & 72-bit ecc revision 1.0 ( tsop-ii ) december. 2003
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 revision history revision 0.0 (february, 2003) - first release revision 0.1 (july, 2003) - deleted speed b3 revision 0.2 (august, 2003) - corrected typo. revision 1.0 (december, 2003) - idd current revision. - finalized
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 samsung electronics co., ltd. reserves the right to change products and specifications without notice. ordering information operating frequencies part number density organization component composition heihgt m383l6523bts-caa/a2/b0/a0 512mb 64m x 72 64mx8( k4h510838b) * 9ea 1,700mil m383l2923bts-caa/a2/b0/a0 1gb 128m x 72 64mx8( k4h510838b) * 18ea 1,700mil m383l2920bts-caa/a2/b0/a0 1gb 128m x 72 128mx4( k4h510438b) * 18ea 1,700mil m383l5628bt1-caa/a2/b0/a0 2gb 256m x 72 st.256mx4( k4h1g0638b) * 18ea 1,700mil M312L6523BTS-CAA/a2/b0/a0 512mb 64m x 72 64mx8( k4h510838b) * 9ea 1,200mil m312l2923bts-caa/a2/b0/a0 1gb 128m x 72 64mx8( k4h510838b) * 18ea 1,200mil m312l2920bts-caa/a2/b0/a0 1gb 128m x 72 128mx4( k4h510438b) * 18ea 1,200mil m312l5628bt0-caa/a2/b0/a0 2gb 256m x 72 st.256mx4( k4h1g0638b) * 18ea 1,200mil aa(ddr266@cl=2) a2(ddr266@cl=2) b0(ddr266@cl=2.5) a0(ddr200@cl=2) speed @cl2 133mhz 133mhz 100mhz 100mhz speed @cl2.5 133mhz 133mhz 133mhz - cl-trcd-trp 2-2-2 2-3-3 2.5-3-3 2-2-2 feature ? power supply : vdd: 2.5v 0.2v, vddq: 2.5v 0.2v ? double-data-rate architecture; two data transfers per clock cycle ? bidirectional data strobe(dqs) ? differential clock inputs(ck and ck ) ? dll aligns dq and dqs transition with ck transition ? programmable read latency 2, 2.5 (clock) ? programmable burst length (2, 4, 8) ? programmable burst type (sequential & interleave) ? edge aligned data output, center aligned data input ? auto & self refresh, 7.8us refresh interval(8k/64ms refresh) ? serial presence detect with eeprom ? 1,700mil / 1,200mil height & double sided 184pin registered dimm based on 512mb b-die (x4, x8)
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 pin configuration (front side/back side) note : 1. * : these pins are not used in this module. 2. pins 111, 158 are nc for 1row module [ m383(12)l6523bts, m383(12)l2920bts ] & used for 2row module [ m383(12)l2923bts, m383(12)l5628bt1(0) ] 3. pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : dm (x8 base module) or dqs (x4 base module). pin front pin front pin front pin back pin back pin back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 vref dq0 vss dq1 dqs0 dq2 vdd dq3 nc /reset vss dq8 dq9 dqs1 vddq *ck1 */ck1 vss dq10 dq11 cke0 vddq dq16 dq17 dqs2 vss a9 dq18 a7 vddq dq19 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 a5 dq24 vss dq25 dqs3 a4 vdd dq26 dq27 a2 vss a1 cb0 cb1 vdd dqs8 a0 cb2 vss cb3 ba1 dq32 vddq dq33 dqs4 dq34 vss ba0 dq35 dq40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 vddq /we dq41 /cas vss dqs5 dq42 dq43 vdd */cs2 dq48 dq49 vss *ck2 */ck2 vddq dqs6 dq50 dq51 vss vddid dq56 dq57 vdd dqs7 dq58 dq59 vss nc sda scl 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 vss dq4 dq5 vddq dm0/dqs9 dq6 dq7 vss nc nc nc vddq dq12 dq13 dm1/dqs10 vdd dq14 dq15 cke1 vddq *ba2 dq20 a12 vss dq21 a11 dm2/dqs11 vdd dq22 a8 dq23 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 vss a6 dq28 dq29 vddq dm3/dqs12 a3 dq30 vss dq31 cb4 cb5 vddq ck0 /ck0 vss dm8/dqs17 a10 cb6 vddq cb7 vss dq36 dq37 vdd dm4/dqs13 dq38 dq39 vss dq44 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 /ras dq45 vddq /cs0 /cs1 dm5/dqs14 vss dq46 dq47 */cs3 vddq dq52 dq53 *a13 vdd dm6/dqs15 dq54 dq55 vddq nc dq60 dq61 vss dm7/dqs16 dq62 dq63 vddq sa0 sa1 sa2 vddspd pin description pin name function pin name function a0 ~ a12 address input (multiplexed) dm0 ~ dm8 data - in mask ba0 ~ ba1 bank select address vdd power supply (2.5v) dq0 ~ dq63 data input/output vddq power supply for dqs(2.5v) dqs0 ~ dqs17 data strobe input/output vss ground ck0, ck0 clock input vref power supply for reference cke0, cke1(for 2 row) clock enable input vddspd serial eeprom power/supply ( 2.3v to 3.6v ) cs0 , cs1 (for 2 row) chip select input sda serial data i/o ras row address strobe scl serial clock cas column address strobe sa0 ~ 2 address in eeprom we write enable nc no connection cb0 ~ cb7 check bit(data-in/data-out) key key
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 512mb, 64m x 72 ecc module (m383(12)l6523bts) (populated as 1 bank of x8 ddr sdram module) functional block diagram v ss d0 - d8 v dd /v ddq d0 - d8 d0 - d8 vref v ddspd spd d0 - d8 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp rcs 0 dqs0 dm0 dm/ cs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 dqs1 dm1 dm/ cs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 dqs 2 dm2 dm/ cs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 dqs3 dm3 dm/ cs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 dqs4 dm4 dm/ cs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 dqs5 dm5 dm/ cs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 dqs6 dm6 dm/ cs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 dqs7 dm7 dm/ cs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 dqs8 dm8 dm/ cs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 d8 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/ cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. pll* ck0, ck0 pck ras cas cke0 ba0-ba1 a0-a12 r e g i s t e r cs0 pck reset rcs0 rba0 - rba1 ra0 - ra12 rras rcas rcke0 rwe ba0 -ba1 : sdrams dq0 - d8 a0 -a12 : sdrams d0 - d8 ras : sdrams d0 - d8 cas : sdrams d0 - d8 cke : sdrams d0 - d8 we : sdrams d0 - d8 we * wire per clock loading table/wiring diagrams
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 1gb, 128m x 72 ecc module (m383(12)l2923bts) (populated as 2 bank of x8 ddr sdram module) functional block diagram rcs 0 dqs0 dm0 dm/ cs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 dqs1 dm1 dm/ cs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 dqs 2 dm2 dm/ cs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 dqs3 dm3 dm/ cs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 dqs4 dm4 dm/ cs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 dqs5 dm5 dm/ cs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 dqs6 dm6 dm/ cs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 dqs7 dm7 dm/ cs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 dm/ cs dqs d9 dm/ cs dqs d10 dm/ cs dqs d11 dm/ cs dqs d12 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm/ cs dqs d13 dm/ cs dqs d14 dm/ cs dqs d15 dm/ cs dqs d16 rcs 1 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref v ddspd spd d0 - d17 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp dqs8 dm8 dm/ cs dqs d8 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 dm/ cs dqs d17 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 pck ras cas cke0 cke1 cs1 ba0-ba1 a0-a12 cs0 we pck reset rcs1 rcs0 rba0 - rba1 ra0 - ra12 rras rcas rcke0 rwe rcke1 ba0 -ba1 : sdrams dq0 - d17 a0 -a12 : sdrams d0 - d17 ras : sdrams d0 - d17 cas : sdrams dq0 - d17 cke : sdrams d0 - d8 cke : sdrams d9 - d17 we : sdrams d0 - d17 r e g i s t e r pll* ck0, ck0 * wire per clock loading table/wiring diagrams notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/ cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms.
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 1gb, 128m x 72 ecc module (m383(12)l2920bts) (populated as 1 bank of x4 ddr sdram module) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dqs0 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dqs9 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dqs13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dqs16 rcs 0 dqs4 dqs1 dqs5 dqs2 dqs3 dqs15 dqs6 dqs7 dq15 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dqs8 dqs17 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm resistors: 22 ohms. ras cas cke0 ba0-ba1 a0-a12 s0 rs0_2 rs0_1 rba0 - rba1 ra0 - ra12 rras rcas rcke0a rwe rcke0b ba0 -ba1 : sdrams dq0 - d17 a0 -a12 : sdrams d0 - d17 ras : sdrams d0 - d17 cas : sdrams dq0 - d17 cke : sdrams d0 - d8 cke : sdrams d9 - d17 we : sdrams d0 - d17 r e g i s t e r dqs i/o 3 i/o 2 i/o 1 i/o 0 d8 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d0 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d1 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d2 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d3 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d4 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d5 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d6 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d7 cs dm vss dqs i/o 3 i/o 2 i/o 1 i/o 0 d17 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d9 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d10 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d11 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d12 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d13 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d14 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d15 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d16 cs dm dqs10 reset pck pck we pll* ck0, ck0 * wire per clock loading table/wiring diagrams a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss d0 - d17 d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref strap: see note 4 v ddspd spd (dm0) (dm1) (dm2) (dm3) (dm4) (dm5) (dm6) (dm7) (dm8) functional block diagram
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dqs0 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm0/dqs9 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm4/dqs13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm7/dqs16 rcs 0 rcs 1 dqs4 dqs1 dqs5 dqs2 dqs3 dm6/dqs15 dqs6 dqs7 dq15 dqs i/o 3 i/o 2 i/o 1 i/o 0 d0 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d1 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d2 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d3 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d4 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d5 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d6 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d7 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d9 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d10 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d11 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d12 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d13 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d14 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d15 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d16 dm dm1/dqs10 v ss dqs i/o 3 i/o 2 i/o 1 i/o 0 d18 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d19 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d20 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d21 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d22 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d23 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d24 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d25 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d27 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d28 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d29 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d30 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d31 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d32 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d33 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d34 dm notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/ cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. ra0 - ra12 a0-an: sdrams d0 - d35 ras : sdrams d0 - d35 rcas cas : sdrams d0 - d35 rcke1 cke: sdrams d18 - d35 pck we : sdrams d0 - d35 rcke0 rba0 - rba1 ba0-ban: sdrams d0 - d35 ras cas cke0 cke1 rcs1 cs1 ba0-ba1 a0-a12 r e g i s t e r rras rwe cs0 rcs0 we pck reset cke: sdrams d0 - d17 pll ck0, ck0 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss d0 - d35 d0 - d35 v dd /v ddq d0 - d35 d0 - d35 vref v ddspd spd 2gb, 256m x 72 ecc module [ m383(12)l5628bt1(0) ] (populated as 2 bank of x4 ddr sdram module) functional block diagram cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dqs8 dm8/dqs17 dqs i/o 3 i/o 2 i/o 1 i/o 0 d8 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d17 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d26 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d35 dm cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd, v ddq -1.0 ~ 3.6 v storage temperature t stg -55 ~ +150 ? c power dissipation p d 1.5 * # of component w short circuit current i os 50 ma permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note : power & dc operating conditions (sstl_2 in/out) notes : 1. includes ?? 25mv margin for dc offset on v ref , and a combined total of ?? 50mv margin for all ac noise and dc offset on v ref , bandwidth limited to 20mhz. the dram must accommodate dram current spikes on v ref and internal dram noise coupled to v ref , both of which may result in v ref noise. v ref should be de-coupled with an inductance of ?? 3nh. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . 4. these parameters should be tested at the pin on actual components and may be checked at either the pin or the pad i n simulation. the ac and dc input specifications are relative to a vref envelop that has been bandwidth limited to 200mhz. recommended operating conditions (voltage referenced to v ss =0v, t a =0 to 70 ? c) parameter symbol min max unit note supply voltage(for device with a nominal v dd of 2.5v) v dd 2.3 2.7 i/o supply voltage v ddq 2.3 2.7 v i/o reference voltage v ref vddq/2-50mv vddq/2+50mv v 1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v 2 input logic high voltage v ih (dc) v ref +0.15 v ddq +0.3 v 4 input logic low voltage v il (dc) -0.3 v ref -0.15 v 4 input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.3 v ddq +0.6 v 3 input leakage current i i -2 2 ua output leakage current i oz -5 5 ua output high current(normal strengh driver) ;v out = v tt + 0.84v i oh -16.8 ma output high current(normal strengh driver) ;v out = v tt - 0.84v i ol 16.8 ma output high current(half strengh driver) ;v out = v tt + 0.45v i oh -9 ma output high current(half strengh driver) ;v out = v tt - 0.45v i ol 9 ma
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 ddr sdram idd spec table (v dd =2.7v, t = 10 ? c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol aa(ddr266@cl=2) a2(ddr266@cl=2) b0(ddr266@cl=2.5) a0(ddr200@cl=2) unit notes idd0 1,620 1,490 1,490 1,490 ma idd1 1,840 1,720 1,720 1,720 ma idd2p 370 350 350 350 ma idd2f 895 770 770 770 ma idd2q 505 480 480 480 ma idd3p 595 570 570 570 ma idd3n 1,080 950 950 950 ma idd4r 1,980 1,850 1,850 1,850 ma idd4w 2,020 1,900 1,900 1,900 ma idd5 2,790 2,660 2,660 2,660 ma idd6 normal 370 350 350 350 ma low power 350 330 330 330 ma optional idd7a 3,670 3,560 3,560 3,560 ma m383(12)l6523bts [ (64m x 8) * 9 , 512mb module ] m383(12)l2923bts [ (64m x 8) * 18 , 1gb module ] (v dd =2.7v, t = 10 ? c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol aa(ddr266@cl=2) a2(ddr266@cl=2) b0(ddr266@cl=2.5) a0(ddr200@cl=2) unit notes idd0 2,190 2,190 2,190 2,190 ma idd1 2,420 2,420 2,420 2,420 ma idd2p 540 540 540 540 ma idd2f 1,290 1,290 1,290 1,290 ma idd2q 810 810 810 810 ma idd3p 990 990 990 990 ma idd3n 1,650 1,650 1,650 1,650 ma idd4r 2,550 2,550 2,550 2,550 ma idd4w 2,600 2,600 2,600 2,600 ma idd5 3,360 3,360 3,360 3,360 ma idd6 normal 540 540 540 540 ma low power 500 500 500 500 ma optional idd7a 4,260 4,260 4,260 4,260 ma
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 ddr sdram idd spec table m383(12)l2920bts [ (128m x 4) * 18 , 1gb module ] m383(12)l5628bt1(0) [ (st.256m x 4) * 18 , 2gb module ] (v dd =2.7v, t = 10 ? c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol aa(ddr266@cl=2) a2(ddr266@cl=2) b0(ddr266@cl=2.5) a0(ddr200@cl=2) unit notes idd0 2,610 2,610 2,610 2,610 ma idd1 3,010 3,010 3,010 3,010 ma idd2p 420 420 420 420 ma idd2f 1,170 1,170 1,170 1,170 ma idd2q 690 690 690 690 ma idd3p 870 870 870 870 ma idd3n 1,530 1,530 1,530 1,530 ma idd4r 3,330 3,330 3,330 3,330 ma idd4w 3,420 3,420 3,420 3,420 ma idd5 4,950 4,950 4,950 4,950 ma idd6 normal 420 420 420 420 ma low power 380 380 380 380 ma optional idd7a 6,750 6,750 6,750 6,750 ma (v dd =2.7v, t = 10 ? c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol aa(ddr266@cl=2) a2(ddr266@cl=2) b0(ddr266@cl=2.5) a0(ddr200@cl=2) unit notes idd0 3,760 3,760 3,760 3,760 ma idd1 4,210 4,210 4,210 4,210 ma idd2p 760 760 760 760 ma idd2f 1,960 1,960 1,960 1,960 ma idd2q 1,300 1,300 1,300 1,300 ma idd3p 1,660 1,660 1,660 1,660 ma idd3n 2,680 2,680 2,680 2,680 ma idd4r 4,480 4,480 4,480 4,480 ma idd4w 4,570 4,570 4,570 4,570 ma idd5 6,100 6,100 6,100 6,100 ma idd6 normal 760 760 760 760 ma low power 680 680 680 680 ma optional idd7a 7,900 7,900 7,900 7,900 ma
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 note : 1. vid is the magnitude of the difference between the input level on ck and the input on ck . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. 3. these parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the ac and dc input specificatims are refation to a vref envelope that has been bandwidth limited 20mhz. output load circuit (sstl_2) output z0=50 ? c load =30pf v ref =0.5*v ddq r t =50 ? v tt =0.5*v ddq input/output capacitance (vdd=2.5v, vddq=2.5v, ta= 25 ? c, f=1mhz) parameter symbol m383(12)l6523bts, m383(12)l2920bts unit min max input capacitance(a0 ~ a12, ba0 ~ ba1, ras , cas , we ) cin1 9 11 pf input capacitance(cke0) cin2 9 11 pf input capacitance( cs 0) cin3 9 11 pf input capacitance( clk0, clk0 ) cin4 11 12 pf input capacitance(dm0~dm8) cin5 10 11 pf data & dqs input/output capacitance(dq0~dq63) cout1 10 11 pf data input/output capacitance (cb0~cb7) cout2 10 11 pf parameter symbol m383(12)l2923bts, m383(12)l5628bt1(0) unit min max input capacitance(a0 ~ a12, ba0 ~ ba1, ras , cas , we ) cin1 9 11 pf input capacitance(cke0,cke1) cin2 9 11 pf input capacitance( cs 0, cs 1) cin3 9 11 pf input capacitance( clk0, clk0 ) cin4 11 12 pf input capacitance(dm0~dm8) cin5 14 16 pf data & dqs input/output capacitance(dq0~dq63) cout1 14 16 pf data input/output capacitance (cb0~cb7) cout2 14 16 pf ac operating conditions parameter/condition symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals vih(ac) vref + 0.31 v 3 input low (logic 0) voltage, dq, dqs and dm signals. vil(ac) vref - 0.31 v 3 input differential voltage, ck and ck inputs vid(ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and ck inputs vix(ac) 0.5*vddq-0.2 0.5*vddq+0.2 v 2 output load circuit (sstl_2) output z0=50 ? c load =30pf v ref =0.5*v ddq r t =50 ? v tt =0.5*v ddq
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 ac timming parameters & specifications parameter symbol aa (ddr266@cl=2) a2 (ddr266@cl=2) b0 (ddr266@cl=2.5) a0 (ddr200@cl=2) unit note min max min max min max min max row cycle time trc 60 65 65 70 ns refresh row cycle time trfc 75 75 75 80 ns row active time tras 45 120k 45 120k 45 120k 48 120k ns ras to cas delay trcd 15 20 20 20 ns row precharge time trp 15 20 20 20 ns row active to row active delay trrd 15 15 15 15 ns write recovery time twr 15 15 15 15 ns last data in to read command twtr 1 1 1 1 tck col. address to col. address delay tccd 1 1 1 1 tck clock cycle time cl=2.0 tck 7.5 12 7.5 12 10 12 10 12 ns cl=2.5 7.5 12 7.5 12 7.5 12 ns clock high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs-out access time from ck/ ck tdqsck -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns output data access time from ck/ ck tac -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns data strobe edge to ouput data edge tdqsq - 0.5 - 0.5 - 0.5 - 0.6 ns 12 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs-in setup time twpres 0 0 0 0 ns 3 dqs-in hold time twpre 0.25 0.25 0.25 0.25 tck dqs falling edge to ck rising-setup time tdss 0.2 0.2 0.2 0.2 tck dqs falling edge from ck rising-hold time tdsh 0.2 0.2 0.2 0.2 tck dqs-in high level width tdqsh 0.35 0.35 0.35 0.35 tck dqs-in low level width tdqsl 0.35 0.35 0.35 0.35 tck dqs-in cycle time tdsc 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck address and control input setup time(fast) tis 0.9 0.9 0.9 1.1 ns i,5.7~9 address and control input hold time(fast) tih 0.9 0.9 0.9 1.1 ns i,5.7~9 address and control input setup time(slow) tis 1.0 1.0 1.0 1.1 ns i, 6~9 address and control input hold time(slow) tih 1.0 1.0 1.0 1.1 ns i, 6~9 data-out high impedence time from ck/ ck thz -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 1 data-out low impedence time from ck/ ck tlz -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 1 input slew rate(for input only pins) tsl(i) 0.5 0.5 0.5 0.5 v/ns input slew rate(for i/o pins) tsl(io) 0.5 0.5 0.5 0.5 v/ns output slew rate(x4,x8) tsl(o) 1.0 4.5 1.0 4.5 1.0 4.5 1.0 4.5 v/ns output slew rate matching ratio (rise to fall) tslmr 0.67 1.5 0.67 1.5 0.67 1.5 0.67 1.5
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 parameter symbol aa (ddr266@cl=2) a2 (ddr266@cl=2) b0 (ddr266@cl=2.5) a0 (ddr200@cl=2) unit note min max min max min max min max mode register set cycle time tmrd 15 15 15 16 ns dq & dm setup time to dqs tds 0.5 0.5 0.5 0.6 ns j, k dq & dm hold time to dqs tdh 0.5 0.5 0.5 0.6 ns j, k control & address input pulse width tipw 2.2 2.2 2.2 2.5 ns 8 dq & dm input pulse width tdipw 1.75 1.75 1.75 2 ns 8 power down exit time tpdex 7.5 7.5 7.5 10 ns exit self refresh to non-read command txsnr 75 75 75 80 ns exit self refresh to read command txsrd 200 200 200 200 tck refresh interval time trefi 7.8 7.8 7.8 7.8 us 4 output dqs valid window tqh thp -tqhs - thp -tqhs - thp -tqhs - thp -tqhs - ns 11 clock half period thp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - ns 10, 11 data hold skew factor tqhs 0.75 0.75 0.75 0.8 ns 11 dqs write postamble time twpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck 2 active to read with auto precharge command trap 20 20 20 20 autoprecharge write recovery + precharge time tdal (twr/tck) + (twr/tck) + (twr/tck) + (twr/tck) + tck 13 system characteristics for ddr sdram the following specification parameters are required in systems using ddr266 & ddr200 devices to ensure proper sys- tem performance. these characteristics are for system simulation purposes and are guaranteed by design. table 1 : input slew rate for dq, dqs, and dm table 2 : input setup & hold time derating for slew rate table 3 : input/output setup & hold time derating for slew rate ac characteristics ddr266 ddr200 parameter symbol min max min max units notes dq/dm/dqs input slew rate measured between vih(dc), vil(dc) and vil(dc), vih(dc) dcslew tbd tbd 0.5 4.0 v/ns a, m input slew rate tis tih units notes 0.5 v/ns 0 0 ps i 0.4 v/ns +50 0 ps i 0.3 v/ns +100 0 ps i input slew rate tds tdh units notes 0.5 v/ns 0 0 ps k 0.4 v/ns +75 +75 ps k 0.3 v/ns +150 +150 ps k
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 table 4 : input/output setup & hold derating for rise/fall delta slew rate table 5 : output slew rate characteristice (x4, x8 devices only) table 6 : output slew rate characteristice (x16 devices only) table 7 : output slew rate matching ratio characteristics delta slew rate tds tdh units notes +/- 0.0 v/ns 0 0 ps j +/- 0.25 v/ns +50 +50 ps j +/- 0.5 v/ns +100 +100 ps j slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g,h pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g,h slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g,h pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g,h ac characteristics ddr266 ddr200 parameter min max min max notes output slew rate matching ratio (pullup to pulldown) tbd tbd 0.67 1.5 e,m
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 system notes : a. pullup slew rate is characteristized under the test conditions as shown in figure 1. output test point vssq 50 ? figure 1 : pullup slew rate test load b. pulldown slew rate is measured under the test conditions shown in figure 2. output test point vddq 50 ? figure 2 : pulldown slew rate test load c. pullup slew rate is measured between (vddq/2 - 320 mv +/- 250 mv) pulldown slew rate is measured between (vddq/2 + 320 mv +/- 250 mv) pullup and pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. example : for typical slew rate, dq0 is switching for minmum slew rate, all dq bits are switching from either high to low, or low to high. the remaining dq bits remain the same as for previous state. d. evaluation conditions typical : 25 ? c (t ambient), vddq = 2.5v, typical process minimum : 70 ? c (t ambient), vddq = 2.3v, slow - slow process maximum : 0 ? c (t ambient), vddq = 2.7v, fast - fast process e. the ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temper ature and voltage range. for a given output, it represents the maximum difference between pullup and pulldown drivers due to process v ariation. f. verified under typical conditions for qualification purposes. g. tsopii package divices only. h. only intended for operation up to 266 mbps per pin. i. a derating factor will be used to increase tis and tih in the case where the input slew rate is below 0.5v/ns as shown in table 2. the input slew rate is based on the lesser of the slew rates detemined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), similarly for rising transitions. j. a derating factor will be used to increase tds and tdh in the case where dq, dm, and dqs slew rates differ, as shown in table s 3 & 4. input slew rate is based on the larger of ac-ac delta rise, fall rate and dc-dc delta rise, input slew rate is based on the lesser of the slew rates determined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), similarly for rising transitions. the delta rise/fall rate is calculated as: {1/(slew rate1)} - {1/(slew rate2)} for example : if slew rate 1 is 0.5 v/ns and slew rate 2 is 0.4 v/ns, then the delta rise, fall rate is - 0.5ns/v . using the table given, this would result in the need for an increase in tds and tdh of 100 ps. k. table 3 is used to increase tds and tdh in the case where the i/o slew rate is below 0.5 v/ns. the i/o slew rate is based on the lesser on the lesser of the ac - ac slew rate and the dc- dc slew rate. the inut slew rate is based on the lesser of the slew rates deter mined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), and similarly for rising transitions. m. dqs, dm, and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal tra nsi tions through the dc region must be monotony.
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 command truth table (v=valid, x=don ? t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we ba0,1 a10/ap a0 ~ a9 a11, a12 note register extended mrs h x l l l l op code 1, 2 register mode register set h x l l l l op code 1, 2 refresh auto refresh h h l l l h x 3 self refresh entry l 3 exit l h l h h h x 3 h x x x 3 bank active & row addr. h x l l h h v row address (a0~a9, a11,a12) read & column address auto precharge disable h x l h l h v l column address 4 auto precharge enable h 4 write & column address auto precharge disable h x l h l l v l column address 4 auto precharge enable h 4, 6 burst stop h x l h h l x 7 precharge bank selection h x l l h l v l x all banks x h 5 active power down entry h l h x x x x l v v v exit l h x x x x precharge power down mode entry h l h x x x x l h h h exit l h h x x x l v v v dm h x x 8 no operation (nop) : not defined h x h x x x x 9 l h h h 9 note : 1. op code : operand code. a 0 ~ a 12 & ba 0 ~ ba 1 : program keys. (@emrs/mrs) 2. emrs/ mrs can be issued only at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functions are same as the cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank b is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. 5. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 7. burst stop command is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and data-in are masked at the both edges (write dm latency is 0). 9. this combination is not defined for any function, which means "no operation(nop)" in ddr sdram.
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 tolerances : 0.005(.13) unless otherwise specified. the used device is 64mx8 ddr sdram, tsopii. ddr sdram part no : k4h510838b physical dimensions : 64m x 72 (m383l6523bts) units : inches (millimeters) a b reg pll reg a b 5.25 0.005 5.171 (131.350) (133.350 0.13 ) ( 4 3 . 3 3 ) 1 . 7 5.077 (128.950) 0 . 3 9 3 ( 1 0 . 0 0 ) 0 . 1 0 0 m i n ( 2 . 3 0 m i n ) (19.80) 0.78 ( 1 7 . 8 0 ) 0 . 7 2.500 0.10 m c b a 0.050 0.0078 0.006 (0.20 0.15) (1.270 ) 0 . 1 0 0 ( 2 . 5 0 ) detail b 0.250 (6.350 ) detail a 0.157 (4.00 ) 0.071 (1.8 0) 0.039 0.002 (1.000 0. 050) (3.80) 2.175 (6.62) 0.26 0.10 m c b a 0.1496 (3.00) 0.118 r (2.00) 0.0787 (4.00) 0.1575 m 0. 157 max 0.050 0.0039 (1.270 0.10) ( 3.99 max) ( 4 . 2 4 ) ( 0 . 1 6 7 ) (3.00) 0.118 r (2.00) 0.0787
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 tolerances : 0.005(.13) unless otherwise specified. the used device is 64mx8, 128mx4, ddr sdram, tsopii. ddr sdram part no : k4h510838b, k4h510438b physical dimensions: 128mx72 (m383l2923bts), 128mx72 (m383l2920bts) units : inches (millimeters) a b reg pll reg a b 5.25 0.005 5.171 (131.350) (133.350 0.13) ( 4 3 . 3 3 ) 1 . 7 5.077 (128.950) 0 . 3 9 3 ( 1 0 . 0 0 ) 0 . 1 0 0 m i n ( 2 . 3 0 m i n ) (19.80) 0.78 ( 1 7 . 8 0 ) 0 . 7 2.500 0.10 m c b a 0.050 0.0078 0.006 (0.20 0.15) (1.270 ) 0 . 1 0 0 ( 2 . 5 0 ) detail b 0.250 (6.350 ) detail a 0.157 (4.00 ) 0.071 (1.8 0) 0.039 0.002 (1.000 0. 050) (3.80) 2.175 (6.62) 0.26 0.10 m c a 0.1496 (3.00) 0.118 r (2.00) 0.0787 (4.00) 0.1575 0.157 max 0.050 0.0039 (1.270 0.10) (3.99 max) ( 4 . 2 4 ) ( 0 . 1 6 7 ) m b (3.00) 0.118 r (2.00) 0.0787
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 physical dimensions: st.256mx72 (m383l5628bt1) units : inches (millimeters) tolerances : 0.005(.13) unless otherwise specified the used device is st.256mx4 sdram, 66tsopii sdram part no. : k4h1g0638b 0.050 0.0078 0.006 (0.20 0.15) (1.270 ) 0 . 1 0 0 ( 2 . 5 0 ) detail b 0.250 (6.350 ) detail a 0.157 (4.00 ) 0.071 (1.8 0) 0.039 0.002 (1.000 0. 050) (3.80) (6.62) 0.26 0.1496 (3.00) 0.118 r (2.00) 0.0787 (4.00) 0.1575 0.10 m c a b m a b reg pll reg a b 5.25 0.005 5.171 (131.350) (133.350 0.13) ( 4 3 . 3 3 ) 1 . 7 5.077 (128.950) 0 . 3 9 3 ( 1 0 . 0 0 ) 0 . 1 0 0 m i n ( 2 . 3 0 m i n ) (19.80) 0.78 ( 1 7 . 8 0 ) 0 . 7 2.500 0.10 m c b a reg 0.268 max 0.050 0.0039 (1.270 0.10) (6.81 max) ( 4 . 2 4 ) ( 0 . 1 6 7 ) 2.175 (3.00) 0.118 r (2.00) 0.0787
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 units : inches (millimeters) tolerances : 0.005(.13) unless otherwise specified the used device is 64mx8 ddr sdram, tsopii sdram part no : k4h510838b a b reg pll a b 5.25 0.005 5.171 (131.350) (133.350 0.13 ) ( 3 0 . 4 8 ) 1 . 2 5.077 (128.950) 0 . 3 9 3 ( 1 0 . 0 0 ) 0 . 1 0 0 m i n ( 2 . 5 0 m i n ) (19.80) 0.78 ( 1 7 . 8 0 ) 0 . 7 2.500 0.050 0.0078 0.006 (0.20 0.15) (1.270 ) 0 . 1 0 0 ( 2 . 5 0 ) detail b 0.250 (6.350 ) detail a 0.157 (4.00 ) 0.071 (1.8 0) 0.039 0.002 (1.000 0. 050) (3.80) 2.175 (6.62) 0.26 0.10 m c b a m 0.1496 (3.00) 0.118 r (2.00) 0.0787 (4.00) 0.1575 0.10 m c b a r (2.00) 0.0787 (3.00) 0.118 reg 0. 157 max 0.050 0.0039 (1.270 0.10) ( 3.99 max) ( 4 . 0 0 ) ( 0 . 1 5 7 ) ( 2 . 3 0 m i n ) physical dimensions : 64m x 72 (m312l6523bts)
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 units : inches (millimeters) tolerances : 0.005(.13) unless otherwise specified the used device is 64mx8, 128mx4 ddrsdram, tsopii sdram part no. : k4h510838b, k4h510438b 0.050 0.0078 0.006 (0.20 0.15) (1.270 ) 0 . 1 0 0 ( 2 . 5 0 ) detail b 0.250 (6.350 ) detail a 0.157 (4.00 ) 0.071 (1.8 0) 0.039 0.002 (1.000 0. 050) (3.80) 2.175 (6.62) 0.26 0.1496 (3.00) 0.118 r (2.00) 0.0787 (4.00) 0.1575 0.10 c b a m m a b reg pll a b 5.25 0.005 5.171 (131.350) (133.350 0.13 ) ( 3 0 . 4 8 ) 1 . 2 5.077 (128.950) 0 . 3 9 3 ( 1 0 . 0 0 ) 0 . 1 0 0 m i n ( 2 . 5 0 m i n ) (19.80) 0.78 ( 1 7 . 8 0 ) 0 . 7 2.500 0.10 m c b a r (2.00) 0.0787 (3.00) 0.118 reg 0. 157 max 0.050 0.0039 (1.270 0.10) ( 3.99 max) ( 4 . 0 0 ) ( 0 . 1 5 7 ) ( 2 . 3 0 m i n ) physical dimensions: 128mx72 (m312l2923bts), 128mx72 (m312l2920bts)
ddr sdram 512mb, 1gb, 2gb tsop registered dimm revison 1.0 december, 2003 units : inches (millimeters) tolerances : 0.005(.13) unless otherwise specified the used device is st.256mx4 sdram, 66tsopii sdram part no : k4h1g0638b a b pll a b 5.25 0.005 5.171 (131.350) (133.350 0.13 ) ( 3 0 . 4 8 ) 1 . 2 5.077 (128.950) 0 . 3 9 3 ( 1 0 . 0 0 ) 0 . 1 0 0 m i n ( 2 . 5 0 m i n ) (19.80) 0.78 ( 1 7 . 8 0 ) 0 . 7 2.500 0.050 0.0078 0.006 (0.20 0.15) (1.270 ) 0 . 1 0 0 ( 2 . 5 0 ) detail b 0.250 (6.350 ) detail a 0.157 (4.00 ) 0.071 (1.8 0) 0.039 0.002 (1.000 0. 050) (3.80) 2.175 (6.62) 0.26 0.10 m c b a m 0.1496 (3.00) 0.118 r (2.00) 0.0787 (4.00) 0.1575 0.10 m c b a r (2.00) 0.0787 (3.00) 0.118 reg. 0.268 max 0.050 0.0039 (1.270 0.10) (6.81 max) ( 4 . 0 0 ) ( 0 . 1 5 7 ) ( 2 . 3 0 m i n ) physical dimensions: st.256mx72 (m312l5628bt0)

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